library verilog;
use verilog.vl_types.all;
entity spi_receiver is
    port(
        clk             : in     vl_logic;
        rst_n           : in     vl_logic;
        spi_cs          : in     vl_logic;
        spi_sck         : in     vl_logic;
        spi_mosi        : in     vl_logic;
        rxd_flag        : out    vl_logic;
        rxd_data        : out    vl_logic_vector(7 downto 0)
    );
end spi_receiver;
